Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 53, Issue 6, Pages 1707-1718Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2018.2796544
Keywords
Sigma Delta noise; finite impulse response (FIR) filter; fractional-N synthesizer; loop bandwidth (BW); phase-locked loop (PLL)
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Funding
- Qualcomm Innovation Fellowship Program
- Broadcom Fellowship Program
- Realtek Semiconductor
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A fractional-N synthesizer architecture incorporates a 35-tap finite impulse response filter that suppresses the Sigma Delta noise, but does not affect the loop bandwidth (BW). Employing a three-stage ring oscillator and operating with a 22.6-MHz reference frequency, the synthesizer achieves a BW of around 5.6 MHz with a power consumption of 10 mW. Realized in 45-nm digital CMOS technology, the synthesizer exhibits a phase noise of -121.4 dBc/Hz at 10-MHz offset and an integrated jitter of 1.5 ps(rms).
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