Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 53, Issue 1, Pages 124-133Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2731813
Keywords
3-bit per cell; 3-D NAND; 64 word-line(WL) stack; cache program; error correction; NAND flash memory; reliability; self IO test; V-NAND
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A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hiding two-page data loading time is presented. This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, a valley tracking read for reducing timing overhead at a read retry is introduced by fast finding optimal read levels. Finally, a high-speed self-test mode for IO operation is presented. The chip, designed with the fourth generation of V-NAND technology, achieved an areal density of 3.98 Gb/mm(2) and operated up to 1 Gb/s at 1.2 V.
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