An Overview of the Development of a GPU with integrated HBM on Silicon Interposer

In recent years, the 2.5D IC (Integrated Circuit) package with TSV (Through Silicon Vias) has become important for high-bandwidth and high-performance applications. It is well known that 2.5D technology requires significant innovation in the areas of process technology, packaging, design, thermals, and test solutions leading to several hundred new technologies in a single product. With these complex material sets and process steps combined with new design requirements, methods, and components, a significant amount of research and engineering development is required to bring a successful product to market. After an 8 year development, in July of 2015 AMD reported it began shipment of a new generation of AMD Radeon (TM) Fury graphics cards, based on the development of the Fiji GPU and the first generation of High Bandwidth Memory (HBM1). This announcement is the next major step in an era for 2.5D IC package technology which will be used in a wide variety of applications. Given the scope of this undertaking many collaborations were required. This paper provides an overview of the collaboration between AMD and ASE. It chronicles the work from initial proof of concept to technology feasibility to product development to production ramp and ultimately high volume production. Details of several functional prototypes are outlined including warpage characterization, stress reduction, materials selection methodologies, and the use of finite element analysis (FEA) and advanced Warpage Metrology Analyzer (WMA) for optimization. The result is a reliable 2.5D process flow with >99% assembly yield for a 1011mm(2) interposer with 5 dies attached in a 300+W 55x55mm(2) package.