Journal
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
Volume 8, Issue 2, Pages 517-532Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TETC.2017.2740364
Keywords
Logic gates; Integrated circuits; Security; Reverse engineering; Layout; IP networks; Boolean functions; Hardware security; logic locking; logic encryption; IC camouflaging; boolean satisfiability; SAT
Funding
- Army Research Office (ARO) [65513-CS]
- US National Science Foundation, Division Of Computer and Network Systems (NSF/CNS) [1652842]
- New York University/New York University Abu Dhabi (NYU/NYUAD) Center for Cyber Security (CCS)
- Direct For Computer & Info Scie & Enginr
- Division Of Computer and Network Systems [1652842] Funding Source: National Science Foundation
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With the adoption of a globalized and distributed IC design flow, IP piracy, reverse engineering, and counterfeiting threats are becoming more prevalent. Logic obfuscation techniques including logic locking and IC camouflaging have been developed to address these emergent challenges. A major challenge for logic locking and camouflaging techniques is to resist Boolean satisfiability (SAT) based attacks that can circumvent state-of-the-art solutions within minutes. Over the past year, multiple SAT attack resilient solutions such as Anti-SAT and AND-tree insertion (ATI) have been presented. In this paper, we perform a security analysis of these countermeasures and show that they leave structural traces behind in their attempts to thwart the SAT attack. We present three attacks, namely signal probability skew (SPS) attack, AppSAT guided removal (AGR) attack, and sensitization guided SAT (SGS) attack, that can break Anti-SAT and ATI, within minutes.
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