Journal
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
Volume 5, Issue 6, Pages 466-472Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JEDS.2017.2752465
Keywords
Nanowire transistor; TCAD; Monte Carlo; vertically stacked
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Funding
- EPSRC [EP/P009972/1]
- European Union Horizon Research and Innovation Program (Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node) [688101]
- Ministry of Higher Education and Scientific Research, Iraq
- Engineering and Physical Sciences Research Council [EP/P009972/1] Funding Source: researchfish
- EPSRC [EP/P009972/1] Funding Source: UKRI
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In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5-nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this paper.
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