Journal
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Volume 5, Issue 1, Pages 213-232Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JESTPE.2016.2605702
Keywords
Multilevel systems; Pareto optimization; power semiconductor devices; reliability
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For power electronic systems to interface medium-voltage grids, e.g., in future electric ships, usually cascaded cells converters need to be employed, whereby either few cells featuring power semiconductors with high blocking voltage capability or a larger number of cells using low-voltage (LV) semiconductors can be used. As shown in this paper, physics-inspired empirical models of the dependence of Insulated-Gate Bipolar Transistor (IGBT) power modules' loss-relevant characteristics on the blocking voltage enable an analytic optimization of the efficiency of a cascaded H-bridges (ac-dc) converter, which is complemented by a full efficiency versus power density eta rho-Pareto optimization. For a 10-kV grid, 1200V or 1700V are identified as optimum blocking voltages, resulting in a suitable trade-off between efficiency and power density. Significant efficiency and power density gains can be realized by replacing silicon IGBTs by LV silicon carbide (SiC) devices in multi-cell systems, whereas single-cell designs based on high-voltage SiC devices suffer from the high dv/dt and di/dt values required to limit switching losses. Reliability is analyzed considering redundancy, showing that the reliability of designs based on lower blocking voltages can be comparable with that of designs using higher blocking voltages, and hence fewer cells, if similar effort concerning additionally installed power capability is considered.
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