ZnO Nanofiber Thin-Film Transistors with Low-Operating Voltages

Although significant progress has been made towards using ZnO nanofibers (NFs) in future high-performance and low-cost electronics, they still suffer from insufficient device performance caused by substantial surface roughness (i.e., irregularity) and granular structure of the obtained NFs. Here, a simple one-step electrospinning process (i.e., without hot-press) is presented to obtain controllable ZnO NF networks to achieve high-performance, large-scale, and low-operating-power thin-film transistors. By precisely manipulating annealing temperature during NF fabrication, their crystallinity, grain size distribution, surface morphology, and corresponding device performance can be regulated reliably for enhanced transistor performances. For the optimal annealing temperature of 500 degrees C, the device exhibits impressive electrical characteristics, including a small positive threshold voltage (V-th) of approximate to 0.9 V, a low leakage current of approximate to 10(-12) A, and a superior on/off current ratio of approximate to 10(6), corresponding to one of the best-performed ZnO NF devices reported to date. When high- AlOx thin films are employed as gate dielectrics, the source/drain voltage (V-DS) can be substantially reduced by 10x to a range of only 0-3 V, along with a 10x improvement in mobility to a respectable value of 0.2 cm(2) V-1 s(-1). These results indicate the potential of these nanofibers for use in next-generation low-power devices.