Short circuit current level reduction in power system by optimal placement of fault current limiter

In this paper, a new methodology is proposed for optimal locations of fault current limiters in the power system to reduce the short circuit (SC) current level at all buses within allowable maximum limit. The proposed methodology is formulated with modification by 2 new techniques. First technique is to modify the search space by using effectiveness value to sort out less effective/dominated candidate locations from the search space by using sensitivity analysis, which is resulted in getting more accurate locations by avoiding local optima and faster results as well. Second technique, ie, an equivalent network representation, is used to reduce the system size and, hence, provides the better result, which is very useful for larger sizes of the power network systems, where chances of the solution stuck at local optima are higher. Further, an optimization tool, ie, genetic algorithm, is used to obtain the best location and size of the fault current limiters. The effectiveness of the proposed approaches are investigated on 3 different network sizes, ie, IEEE 30-bus, New England 39-bus, and a practical large Vietnamese 1360-bus systems to ensure robustness and suitability of the method. The obtained results are compared and found to be better than method suggested in the literature works.