A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops

In this paper, a new charge pump circuit for reducing charge and discharge currents with low power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump generates maximum 19.9 A current. This charge pump is designed and simulated in TSMC 0.18 m CMOS technology in order to be used in a delay-locked loop. One of the benefits of this circuit is its capability to be applied in a wide frequency range from 50 to 800 MHz with power consumption range of 410-740 W. The proposed charge pump exploits feedback loop in order to achieve suitable current matching and also has a good characteristics in high frequencies.