Low Power and Small Area, 6.9 ps RMS Time-to-Digital Converter for 3-D Digital SiPM

Time-of-flight measurements are becoming essential to the advancement of several fields, such as preclinical positron emission tomography and high energy physics. Recent developments in single photon avalanche diode (SPAD)-based detectors have spawned a great interest in digital silicon photomultipliers (dSiPMs). To overcome the tradeoff between the photosensitive area and the processing capabilities in current 2-D dSiPM, we propose a novel 3-D digital SiPM, where the SPAD, designed for maximal photosensitive area, will be stacked in 3-D over the electronic circuits, designed in a CMOS node technology. All readout circuits will be implemented directly under the SPAD real estate, including quenching circuit, time-to-digital converter (TDC) and digital readout electronics. This paper focusses on the TDC element of this system, designed in TSMC CMOS 65 nm. This ring oscillator-based Vernier TDC requires only 25 x 50 mu m(2) and 160 mu W, and achieves 6.9 ps rms timing accuracy.