Journal
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
Volume 79, Issue -, Pages 301-306Publisher
ELSEVIER GMBH, URBAN & FISCHER VERLAG
DOI: 10.1016/j.aeue.2017.06.022
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We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 035 urn CMOS technology, an extra current flows into the circuit only when an input voltage variation occurs (through the adaptive biasing technique), so improving the transient response speed without a substantial increase of the average power consumption. Simulation results confirm the expected theoretical considerations. (C) 2017 Elsevier GmbH. All rights reserved.
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