Journal
2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Volume -, Issue -, Pages -Publisher
IEEE
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Funding
- NRF Singapore through the SMART-LEES IRG
- MOE [R-263-000-C58-133]
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An approach for heterogeneous integration of InGaAs MOSHEMTs and Si-CMOS is proposed and a high quality multi-layer transfer process is demonstrated in 200 mm wafer scale. Heterostructures for In0.30Ga0.70As MOSHEMTs were grown using MOCVD on 200 mm Si substrates with record low threading dislocation density of < 2 x 10(7) cm(-2). Devices with a Si-CMOS compatible front-end process were fabricated and the impact of the heterostructure design and doping on device performance is studied. Low subthreshold swing with minimum (S-min) down to 70 mV/decade was achieved by employing an InGaP top barrier layer and a cap doping of similar to 2 x 10(19) cm(-3) was obtained with a Si-Te co-doping technique. An effective mobility (mu(eff)) of similar to 4900 cm(2)/V.s at sheet electron density (N-s) of 3 x 10(12) cm(-2) was achieved which is record among InxGa1-x As (x <= 0.53) MOSFETs on Si substrates. In addition, current-gain cut-off frequency (f(T)) of similar to 60 GHIz was extracted for 150 nm channel length MOSHEMTs.
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