Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations

3D Finite Element (FE) Monte Carlo (MC) simulation toolbox incorporating 2D Schrodinger equation quantum corrections is employed to simulate I-D-V-G characteristics of a 22 nm gate length gate-all-around (GM) Si nanowire (NW) FET demonstrating an excellent agreement against experimental data at both low and high drain biases. We then scale the Si GM NW according to the ITRS specifications to a gate length of 10 nm predicting that the NW FET will deliver the required on-current of above 1 mA/mu m and a superior electrostatic integrity with a nearly ideal sub-threshold slope Of 68 mV/dec and a DIBL of 39 mV/V. In addition, we use a calibrated 3D FE quantum corrected drift-diffusion (DD) toolbox to investigate the effects of NW line-edge roughness (LER) induced variability on the subthreshold characteristics (threshold voltage (V-T), OFF-current (I-OFF), sub-threshold slope (SS) and drain induced -barrier-lowering (DIBL)) for the 22 nm and 10 nm gate length GM NW FETs at lbw and high drain biases. We simulate variability with two LER correlation lengths (CL = 20 nm and 10 nm) and three root mean square values (RMS = 0.6, 0.7 and 0.85 nm). (C) 2016 Elsevier Ltd. All rights reserved.