Trapping mechanisms in insulated-gate GaN power devices: Understanding and characterization techniques

In addition to surface- and buffer-trapping, interface/border trapping and the consequent V-TH shift in insulated-gate GaN power transistors could also cause R-ON increase, due to the reduced gate overdrive. This work reports on a systematic study of the trapping mechanisms in normally-on/off insulated-gate GaN transistors subjected to dynamic (AC) and static (DC) gate stress. The fast dynamic characterizations featuring an ultrashort measurement delay of 10(-7)s minimize the recovery during measurement and enable a quantitative evaluation of V-TH shift-induced R-ON increase. By analyzing the time-resolved instability in normally-on MIS-HEMT and normally-off MIS-FET with fully recessed barrier, we elucidate several key mechanisms including: (i) recessing the polarized III-nitride barrier layer can suppress V-TH shift during ON/OFF switching; (ii) AC stress, which has more practical implication for lifetime projection for power switching applications, produces smaller V-TH shift and R-ON increase comparing to DC stress; (iii) Sufficient gate overdrive at ON state and lower channel resistance in normally-on MIS-HEMT allow a better tolerance to V-TH shift. Primary trapping effects in an insulated-gate GaN power transistor.