Journal
IEEE SOLID-STATE CIRCUITS LETTERS
Volume 1, Issue 9, Pages 190-193Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LSSC.2019.2906777
Keywords
0.2V; analog-to-digital converter (ADC); deep-subthreshold; IoT; nonlinear; quantization (Q)-noise; ultralow voltage (ULV); voltage-controlled oscillator (VCO)-based ADC
Funding
- Science Foundation Ireland [14/RP/I2921]
- Marie Sklodowska-Curie Actions [747585]
- Marie Curie Actions (MSCA) [747585] Funding Source: Marie Curie Actions (MSCA)
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We present a 0.2-V open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) intended for IoT wireless sensor nodes. A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a reconfigurable input range, allowing it to exceed the supply by 2.5x (single-ended), and maintaining tolerance against +/- 10% supply variations. Latch, flip-flops, and logic gates within the frequency-to-digital converter are designed for minimum propagation delays, allowing sampling at 30 MS/s. The ADC is implemented in 28-nm CMOS and achieves a peak SNDR of 68 dB, equivalent to an ENOB of 11, over a 61-kHz bandwidth with a 1-V-pp input differential sinewave. It consumes 7 mu W, resulting in a state-of-the-art Walden and Schreier FoM of 27.8 fJ/c-s and 167.4 dB, respectively.
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