Journal
2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)
Volume -, Issue -, Pages 257-262Publisher
IEEE
DOI: 10.1109/ISVLSI.2018.00055
Keywords
Single-Electron Transistor (SET); SET Array Blocks (SAB); delay minimization synthesis flow
Categories
Funding
- Ministry of Science and Technology of Taiwan [MOST 106-2221-E-007-111-MY3, MOST 103-2221-E-007-125-MY3]
- MEDIATEK Research Center Doctoral Talent Fellowship
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Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.
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