Journal
MICROELECTRONICS JOURNAL
Volume 61, Issue -, Pages 43-50Publisher
ELSEVIER SCI LTD
DOI: 10.1016/j.mejo.2017.01.001
Keywords
Charge sharing; Single event double-upset; Single event transient; Single event upset; Radiation hardening
Funding
- Anhui University Doctor Startup Fund [J01003217]
- National Natural Science Foundation of China [61604001, 61574052, 61474036]
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Technology scaling results in that, single event effects, such as single event double-upset due to double-node charge sharing, and single event transient (i.e. an invalid pulse) propagated from upstream combinational blocks, are becoming increasingly serious with technology evolution. In this paper, a single event double-upset fully immune and single event transient filterable latch is proposed in 65 nm CMOS technology. By means of a triple-input Muller C-element, which is driven through a clock gating based triple path DICE, all internal nodes and output node of the latch not only self-recover from single event upset regardless of the energy of a striking particle, but also tolerate single event double-upset when any arbitrary combination of the node pairs is affected. Further, taking advaritage of a keeper connected to the output node, the latch is insensitive to a high impedance state. Besides, making use of an embedded Schmitt trigger inverter on the propagation path, the latch also effectively filters single event transient. Simulation results have demonstrated the single event double-upset fully immunity, single event transient filterability, and cost effectiveness, i.e. approximate 60.41% area-power-delay product saving for the latch, compared with the single event double-upset fully immune DNCS-SEI latch, which cannot filter single event transient at all.
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