Journal
IEEE ACCESS
Volume 7, Issue -, Pages 38035-38043Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/ACCESS.2019.2905767
Keywords
Cascaded phase-locked loop; charge pump; leakage current; phase-locked loop; reference spur
Categories
Funding
- IC Design Education Center (IDEC)
- Ministry of Trade, Industry Energy (MOTIE)
- Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor device
- BK21 program, South Korea
Ask authors/readers for more resources
This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead. This leakage compensation loop senses the leakage current of the loop filter from the up and down pulse widths in the steady state and compensates for the charge loss due to the leakage current. A systematic approach for the reference spur reduction is also proposed. Since a PLL operates as a band pass filter in the frequency domain, the reference spur can be filtered out by cascading the PLLs. The optimization technique for the cascaded PLLs is presented that minimizes the reference spur without degrading the phase noise performance. The proposed techniques are verified using an 800-MHz PLL chip fabricated in 65-nm CMOS process. The prototype PLL achieves the reference spur of -68.57 dBc while the conventional charge-pump PLL without the proposed spur reduction techniques achieves -42.83 dBc.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available