Improving the Scalability of SOI-Based Tunnel FETs Using Ground Plane in Buried Oxide

Tunnel field-effect transistors (TFETs) are known to exhibit degraded electrical characteristics at smaller channel lengths, primarily due to direct source-to-drain band-to-band tunneling (BTBT). In this paper, we propose a technique to suppress direct source-to-drain BTBT by increasing the effective distance between the source and the drain. We propose to add a ground plane (GP) in the buried oxide of a silicon-on-insulator (SOI) TFET which depletes the drain and increases the effective source-to-drain distance. Using 2-D device simulations it is shown that the introduction of the ground plane is effective in reducing OFF-state current and ambipolar current, as well as, in improving the average subthreshold swing for the small channel length SOI-TFETs. Additionally, the addition of GP is helpful in ameliorating the short-channel effects, such as drain-induced barrier lowering and threshold voltage roll-off.