Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage

In this work, we aim to maintain the correct execution of instructions in the pipeline stages. To achieve that, the integrity for the data computed in registers during execution should be maintained via protecting the susceptible registers. Thus, we present a Double Node Upset Resilient Flip-Flop (DNUR-FF) circuit that can tolerate double errors while incurring low area and power overheads. We deploy the proposed soft-error resilient register at higher level to replace the most vulnerable registers in large-scale pipeline processors. The experimental results validate the robustness of our design by delivering superior fault coverage masking (100%) for both SEU and DNU errors. In addition, the proposed design utilizes partial spatial redundancy, and therefore, incurs reduced area overhead (31%) and realizes 58% of PDP improvement compared to Triple Module Redundancy (TMR) approach while delivering high-performance with low complexity and power consumption.