Strained Si on Insulator as Potential Material for Forced Stacked Multi-threshold FinFET Based Inverter Considering Ultra Low-Power Applications

This work investigates the performance of strained Si on insulator as potential material for forced stacked multi-threshold FinFET based inverter considering its ultra low-power applications. Using the calibrated exhaustive 3D-TCAD mixed-mode simulation a comparative analysis of conventional and forced stack FinFET based inverters has been performed. The static and dynamic characteristics have been compared with conventional and forced stacked FinFET based inverter. The leakage in standby mode can be reduced through well-defined stack and multi-threshold (V-TH) transistors. Channel doping is optimized to get higher V-TH devices. To improve the speed of circuits FinFETs are designed on strained Silicon on Insulator (sSOI) wafer. Uniform uniaxial tensile stress in sSOI gives the advantage of high ON current in n-FinFETs. It is observed that using strained FinFETs the maximum delay is reduced below 10 ps and using multi V-TH forced stack technique the leakage power is reduced. Hence, forced stack technique based FinFET can evolve as a potential candidate for the future ultra-low power device applications.