Journal
IEEE ACCESS
Volume 7, Issue -, Pages 126479-126488Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/ACCESS.2019.2938737
Keywords
Digital to analog converter (DAC); automated design; calibration; fully synthesizable; fully digital; ultra-low design effort; standard-cell-based analog circuits
Categories
Funding
- Singapore Ministry of Education [MOE2014-T2-2-158]
- European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant [703988]
- Marie Curie Actions (MSCA) [703988] Funding Source: Marie Curie Actions (MSCA)
Ask authors/readers for more resources
In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming 50.8/mu W, the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45/mu W power, at only 530 mu m(2) area.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available