3.8 Proceedings Paper

BMC for Weak Memory Models: Relation Analysis for Compact SMT Encodings

Journal

COMPUTER AIDED VERIFICATION, CAV 2019, PT I
Volume 11561, Issue -, Pages 355-365

Publisher

SPRINGER INTERNATIONAL PUBLISHING AG
DOI: 10.1007/978-3-030-25540-4_19

Keywords

Weak memory models; CAT; Concurrency; BMC; SMT

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We present DARTAGNAN, a bounded model checker (BMC) for concurrent programs under weak memory models. Its distinguishing feature is that the memory model is not implemented inside the tool but taken as part of the input. DARTAGNAN reads CAT, the standard language for memory models, which allows to define x86/TSO, ARMv7, ARMv8, POWER, C/C++, and LINUX kernel concurrency primitives. BMC with memory models as inputs is challenging. One has to encode into SMT not only the program but also its semantics as defined by the memory model. What makes DARTAGNAN scale is its relation analysis, a novel static analysis that significantly reduces the size of the encoding. DARTAGNAN matches or even exceeds the performance of the model-specific verification tools NIDHUGG and CBMC, as well as the performance of HERD, a CAT-compatible litmus testing tool. Compared to the unoptimized encoding, the speed-up is often more than two orders of magnitude.

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