Journal
2019 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)
Volume -, Issue -, Pages -Publisher
IEEE
DOI: 10.1109/CICC.2019.8780362
Keywords
SSCG; two-point modulation; calibration-free; bang-bang; nested-loop; two-stage; DTC
Categories
Funding
- Tsinghua-Samsung joint research project
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This paper describes a calibration-free two-point modulation method for spread-spectrum clock generators (SSCGs) by utilizing a two-stage nested-loop BBPLI, architecture. Having a 1-bit TDC and an absolute-gain DCO, the two-point modulation based on the nested-loop BBPLL does not suffer from nonlinearity of the TDC and the DCO. A prototype 5GHz SSCG is implemented in 65nm CMOS. The proposed SSCG achieves a clock power reduction of 26dB with 200kHz modulation frequency and 5000ppm frequency spread, consuming 9mW with 1V supply.
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