3.8 Proceedings Paper

Design Considerations of DSP-based SiC-MOSFET SAPF with 100kHz Sampling and Switching Frequency

Journal

Publisher

IEEE
DOI: 10.1109/ecce.2019.8912256

Keywords

shunt active power filter; high bandwidth; dual-core system; parallel digital signal processing

Funding

  1. National Natural Science Foundation of China [51277086]

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In this paper, a unique 100kHz sampling and switching frequency shunt active power filter (SAPF), which is based on a dual-core DSP TMS320F28377D, is designed to achieve high control bandwidth for the potential market of wide frequency range harmonic suppression and resonance damping in future more electric aircraft (MEA) or high-speed railway power grid. By rearranging different computation segments, such as analog-to-digital conversion, recursive discrete Fourier transform (RDFT), inner-loop current and outer-loop voltage control, the traditional single pipeline code structure in DSP can be reformed as two parallel running groups. This multitasking strategy provides the proposed SAPF with huge advantages on higher frequency harmonic suppression compared to the mostly commercial SAPF with 10 similar to 20kHz switching frequency. Detailed parameter design of LCL filter, DC-side capacitor and deadtime are also presented. A 10kVA prototype utilizing CREE SiC power module CCS050M12CM2 is set up to verify the effectiveness of the proposed SAPF. The results show that the total harmonic distortion can be limited within 5%, which complies with the IEEE power quality standard 519-2014.

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