Journal
2019 SYMPOSIUM ON VLSI CIRCUITS
Volume -, Issue -, Pages C300-C301Publisher
IEEE
DOI: 10.23919/vlsic.2019.8778056
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Funding
- U.S. Government under the DARPA CRAFT program
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This work presents a scalable deep neural network (DNN) accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic die are limited to specific network sizes, the proposed architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. The 16nm prototype achieves 1.29 TOPS/mm(2), 0.11 pJ/op energy efficiency, 4,01 TOPS peak performance for a I chip system, and 127.8 peak TOPS and 2615 images/s ResNet-50 inference for a 36-chip system.
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