Journal
2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019)
Volume -, Issue -, Pages 461-466Publisher
IEEE COMPUTER SOC
DOI: 10.1109/ISVLSI.2019.00089
Keywords
Image Sensor; Visual Attention; Neuromorphic; FPGA; Predictive Coding
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This paper presents a pixel parallel architecture of a neuromorphic image sensor, designed as a 3D bottom-up architecture composing of several computational planes where each plane performs different image processing algorithms. The model emulates the hierarchical process in biological vision by providing feedforward and feedback information flow between different planes. The on-chip attention module dynamically detects regions with relevant information and produces a feedback path to sample those regions with a higher clock frequency, whereas regions with low spatial and temporal information receive less attention. The results suggest that by sampling non-relevant regions with a lower frequency, the sensor can reduce redundancy and enable high-performance computing at low power. Furthermore, by deploying high-level reasoning only on the selected regions instead of the entire image the model can decrease computational expenses.
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