Journal
IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume 18, Issue -, Pages 999-1004Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2019.2942456
Keywords
Moore's Law; VLSI Technology; CMOS Scaling; FinFET; Contacted-Gate-Pitch (CGP); Fin-Pitch; Contact Resistivity; Contact Resistance
Ask authors/readers for more resources
Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It is concluded that the combined requirements of device electrostatics together with the demands on contact resistance, presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs. FET drive is expected to significantly degrade below this CGP similar to 40 nm as a result. Good agreement between hardware data and TCAD simulations is achieved and employed to estimate the contact resistance values for aggressively scaled FinFETs. These observations show that FinFETs scaled below CGP of 40 nm will require the contact resistivity (rho(C)) of similar to 8 x 10(-10) O-cm(2), while fully ohmic contacts i.e., rho(C) of similar to 1 x 10(-10) O-cm(2) will be required if FinFETs are to extend performance below CGP of 30 nm. Ultimately, transition to new device architectures in which contact area is independent of CGP and/or Fin-Pitch will be necessary.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available