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2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Volume -, Issue -, Pages -Publisher
IEEE
DOI: 10.1109/iedm19573.2019.8993570
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Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.
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