3.8 Proceedings Paper

A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLL

Journal

Publisher

IEEE
DOI: 10.1109/a-sscc47793.2019.9056890

Keywords

phase-locked loop; frequency modulation; 00K; FSK; FOOK; two-point modulation; transimitter

Funding

  1. NSFC [61774092]

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This paper presents an energy-efficient high data rate constant-envelope modulator by employing a binary frequency-domain on-off keying (BFOOK) method. Thanks to the fully-balanced FSK feature high data rate BFOOK modulation is performed based on an integer-N hybrid PLL with VCO modulation only. A carrier spreading technique based on low-frequency wideband triangular modulation can also be added as an optional fractional-N mode in case carrier power suppression is needed to have better spectrum compliance. A prototype 3.5GHz modulator is implemented in 65nm CMOS. The BFOOK modulator achieves the maximum data rate of 100Mb/s maintaining averaged center frequency regardless of the data pattern. The modulator consumes 9.6mW from a 1V supply achieving the energy efficiency of 96pJ/b.

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