Journal
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
Volume 32, Issue 2, Pages 297-311Publisher
SCIENCE PRESS
DOI: 10.1007/s11390-017-1723-1
Keywords
power and area optimization; Reed-Muller (RM) circuit; Pareto optimal solution; don't care term; chromosome conversion
Funding
- National Natural Science Foundation of China [60973106, 61370059, 61232009, 81571142]
- Beijing Natural Science Foundation [4152030]
- Fundamental Research Funds for the Central Universities of China [YWF-15-GJSYS-085, YWF-14-JSJXY-14]
- Fund of the State Key Laboratory of Computer Architecture of China [CARCH201507]
- Open Project Program of National Engineering Research Center for Science and Technology Resources Sharing Service (Beihang University)
- Fund of the State Key Laboratory of Software Development Environment of China [SKLSDE-2016ZX-15]
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The power and area optimization of Reed-Muller (RM) circuits has been widely concerned. However, almost none of the exiting power and area optimization approaches can obtain all the Pareto optimal solutions of the original problem and are efficient enough. Moreover, they have not considered the don't care terms, which makes the circuit performance unable to be further optimized. In this paper, we propose a power and area optimization approach of mixed polarity RM expression (MPRM) for incompletely specified Boolean functions based on Non-Dominated Sorting Genetic Algorithm II (NSGA-II). Firstly, the incompletely specified Boolean function is transformed into zero polarity incompletely specified MPRM (ISMPRM) by using a novel ISMPRM acquisition algorithm. Secondly, the polarity and allocation of don't care terms of ISMPRM is encoded as chromosome. Lastly, the Pareto optimal solutions are obtained by using NSGA-II, in which MPRM corresponding to the given chromosome is obtained by using a chromosome conversion algorithm. The results on incompletely specified Boolean functions and MCNC benchmark circuits show that a significant power and area improvement can be made compared with the existing power and area optimization approaches of RM circuits.
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