Tunable band alignment and dielectric constant of solution route fabricated Al/HfO2/Si gate stack for CMOS applications

The solution route deposition method will reduce the fabrication cost, and it is compatible with existing Si technology. Here, we systematically investigate the impact of annealing temperature on the electrical and dielectric properties along with the band alignment of HfO2 thin films with silicon. The films were fabricated using the hafnium isopropoxide adduct precursor, which is environment friendly and non-toxic in ambient conditions. We have analyzed the band alignment of HfO2/Si stack by using ultra-violet photoelectron spectroscopic and current-voltage (J- V) plot to understand its impact on electrical transport. The bandgap of HfO2 films estimated from Plasmon energy loss spectra is 5.9 eV. The composition analysis is done with X-ray photoelectron spectroscopy that suggests a good stoichiometric ratio of 1: 1.96. The atomic force microscopy studies display a smooth surface with the roughness of 1.4 angstrom without any cracks in the films. It is found that the current conduction mechanisms and barrier heights at both the interfaces are influenced by the annealing temperature; a temperature of 450 degrees C results in an optimum performance. Interestingly, the high value of dielectric constant ( 23) in the amorphous phase is attributed to the existence of cubic like short range order in HfO2 films. Moreover, a low leakage current density of 1.4 Chi 10(-9) A/cm(2) at -1V and 1.48 Chi 10(-8) A/cm2 at +1V in gate and substrate injection modes is achieved. The obtained defect activation energies of 0.91 eV, 0.87 eV, and 0.93 eV for the films annealed at 350 degrees C, 450 degrees C, and 550 degrees C lay below the conduction band edge of HfO2. These energy levels are ascribed to three and four fold oxygen vacancy related traps. The formation of dipoles at the interface, change in the microstructure, and oxygen migration at the interfacial layer are the possible causes for the observed parametric variations in the metal-insulator-semiconductor structure. The electrical properties can be tuned by utilizing suitable annealing temperatures.