Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 55, Issue 6, Pages 1733-1743Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2019.2963616
Keywords
Random access memory; Hardware; System-on-chip; Transistors; Computer architecture; Neural networks; Complexity theory; Binary weights; deep neural networks (DNNs); ensemble learning; in-memory computing (IMC); SRAM; ternary activations
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Funding
- NSF [1652866]
- Wei Family Private Foundation
- Catalyst Foundation
- Center for Brain-Inspired Computing (C-BRIC), one of six centers in JUMP, a Semiconductor Research Corporation (SRC) Program - Defense Advanced Research Projects Agency (DARPA)
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We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep neural networks (DNNs) without row-by-row data access. The XNOR-SRAM bitcell embeds circuits for ternary XNOR operations, which are accumulated on the read bitline (RBL) by simultaneously turning on all 256 rows, essentially forming a resistive voltage divider. The analog RBL voltage is digitized with a column-multiplexed 11-level flash analog-to-digital converter (ADC) at the XNOR-SRAM periphery. XNOR-SRAM is prototyped in a 65-nm CMOS and achieves the energy efficiency of 403 TOPS/W for ternary-XAC operations with 88.8% test accuracy for the CIFAR-10 data set at 0.6-V supply. This marks 33x better energy efficiency and 300x better energy-delay product than conventional digital hardware and also represents among the best tradeoff in energy efficiency and DNN accuracy.
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