Journal
IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume 19, Issue -, Pages 613-619Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2020.3012669
Keywords
Computer architecture; Microprocessors; Magnetic tunneling; Writing; Resistance; Transistors; Random access memory; MRAM; SOT-MTJ; SOT-MRAM; MLC; SLC
Categories
Funding
- SpOT-LITE program (A*STAR) through RIE2020 funds from Singapore SINGA A*Star [A18A6b0057]
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This paper proposes a novel multi-level cell spin-orbit torque magnetic random-access memory (MLC SOT-MRAM) cell structure and validates its functionality and performance through simulation. The proposed memory cell comprises two uniform magnetic tunnel junctions (MTJs) that can be programmed separately by the energy efficient SOT technology through two different heavy metal electrodes. This permit employing both single and dual port architectures. The uniform cross-sectional area of the in-series MTJs stack simplifies the fabrication process. In addition, the cell structure requires only four terminals to successfully read and write the two bits. This allows accessing the two bits with only three access transistors, which achieves 25% smaller 1-bit effective area compared to the conventional single level cell (SLC) SOT-MRAM that requires four transistors. Simulation results based on an approximated dynamic model shows it offers nearly similar write energy consumption compared to the conventional SOT-MRAM.
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