Journal
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS
Volume 56, Issue 5, Pages 3931-3940Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TAES.2020.2982341
Keywords
Latches; Transient analysis; Clocks; Logic gates; Transistors; Redundancy; Radiation hardening (electronics); Circuit reliability; double-upset; low power; soft error; transient pulse
Funding
- National Natural Science Foundation of China [61974001, 61874156, 61674048, 61904001, 61872001, 61834006]
- Anhui University Doctor Startup Fund [Y040435009]
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To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.
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