Journal
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 64, Issue 11, Pages 8747-8755Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2017.2703688
Keywords
Field-programmable gate array (FPGA); geometric algebra; image processing
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Funding
- National Council of Science and Technology (CONACyT), Mexico
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This paper presents an implementation of the conformal voting scheme using a reconfigurable hardware approach in the frame of conformal geometric algebra G(3,1). This algorithm is able to extract geometric entities, such as circles and lines from edged images. The conformal voting scheme is divided into two main stages: a local stage computed using neighborhoods in the image, and a global stage using the results of the local voting stage. In this implementation, we focused on the most computationally demanding stage: the local stage, which is computed in the field-programmable gate array, while the global voting stage continues to be executed on the PC. The results show an average speedup of 3x depending on the features of the input image and a coefficient of variation near to zero in the times of repeated experiments. Finally, our method can be used for multiple applications in real-time image processing.
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