Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 64, Issue 12, Pages 4928-4936Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2017.2766046
Keywords
Compact model; cross-point array; Monte Carlo (MC); nonvolatile memory; resistive random access memory (RRAM); SPICE; statistical analysis; variability
Funding
- Stanford Non-Volatile Memory Technology Research Initiative
- Stanford Non-Volatile Memory Technology Research Initiative, STARnet SONIC, the NCN-NEEDS Program within the National Science Foundation [1227020-EEC]
- Semiconductor Research Corporation
- National Natural Science Foundation of China [61421005, 61334007]
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Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance.
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