Leakage Current and Low-Frequency Noise Analysis and Reduction in a Suspended SOI Lateral p-i-n Diode

In this paper, we present a detailed analysis of leakage current in a silicon-on-insulator (SOI) lateral P+P-N+ (p-i-n) diode suspended on a microheating platform, combining device experimental characterization and numerical simulation. The diode leakage currents have been extensively studied using the back-gate bias as a means to alter the space-charge (SC) condition at the P-region (I-region)/buried oxide interface from accumulation to full depletion, and finally to inversion. Both dark leakage current analysis and low-frequency noise characterization performed on the suspended SOI lateral p-i-n diode indicate device degradation induced by micro-electromechanical systems postprocessing (i.e., deep reactive-ion etching or aluminum deposition). A low-temperature (similar to 250 degrees C) in situ (i.e., using embedded microheater) annealing of SOI lateral p-i-n diode after postprocessing allows reduction of the diode leakage current and optimization of the device performance by neutralizing the interface traps and improving carriers' lifetime and surface recombination velocity. Numerical simulations have been performed with Atlas/SILVACO for deeper analysis of the leakage current behavior in the lateral p-i-n diode and identification of the generation mechanism dominating the diode leakage behavior. Simulation reveals that the dominant generation rate in the diode depends on the SC conditions, the interface trap density, and the carriers' lifetime in the I-region. The experimental and simulated behaviors of as processed and annealed diode leakage current are shown to be in good qualitative agreement.