Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 64, Issue 7, Pages 3037-3040Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2017.2707664
Keywords
Ferroelectric FET (FeFET); nonvolatile computing; nonvolatile SRAM (nvSRAM); power gating; SRAM
Funding
- GRC [2657.001]
- NSF [CCF-1409798, KK1522]
- ASSIST
- NSFC [61674094]
- Center for Low Energy Systems Technology, one of the six SRC STARnet Centers - MARCO
- DARPA
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Nonvolatile SRAM (nvSRAM) has emerged as a promising approach to reducing the standby energy consumption by storing the state into an in situ nonvolatile memory element and shutting down the power supply. Existing nvSRAM solutions based on a nonvolatile backup in magnetic tunnel junction and ReRAM, however, are costly in backup and restore energy due to static current. This cost results in a long breakeven time (BET) when compared with a lowered voltage standby volatile SRAM. This brief proposes an nvSRAM based on ferroelectric FETs (FeFETs) that are capable of fully avoiding such static current. A simple differential backup and restore circuitry is proposed, achieving sub-fJ/cell total energy per backup and restore operation at the 10-nm node. This leads to hundreds of times BET improvement over existing ReRAM nvSRAM solutions. This nvSRAM also indicates the future FeFET design trends for such memory-logic synergy.
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