Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 64, Issue 3, Pages 329-333Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2016.2568181
Keywords
Bernoulli map; discrete time chaos (DTC); integrated circuit; tent map; true random number generator (TRNG)
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Funding
- Bogazici University Research Fund [BAP-6517]
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In this brief, we present the first integrated circuit implementation of our previously proposed dual entropy core true-random-number-generator architecture, which is designed following a novel parameter variation-aware approach. A prototype integrated circuit has been fabricated in 180-nm CMOS technology. The prototype chip achieved a 35-Mbps throughput with an approximately 33-pJ/b energy efficiency. Random numbers acquired from the prototype chip have successfully passed all National Institute of Standards and Technology 800.22 statistical tests without requiring any postprocessing.
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