4.7 Article

An Energy-Efficient Frequency-Domain CMOS Temperature Sensor With Switched Vernier Time-to-Digital Conversion

Journal

IEEE SENSORS JOURNAL
Volume 17, Issue 10, Pages 3001-3011

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSEN.2017.2686442

Keywords

Frequency domain; temperature sensor; time-to-digital converter

Funding

  1. Ministry of Science, ICT and Future Planning [R7117-16-0165]
  2. Industrial Core Technology Development Program Development of Fusion Power Management Platforms and Solutions for Smart Connected Devices - Ministry of Trade, Industry and Energy [10049095]
  3. Institute for Information & Communication Technology Planning & Evaluation (IITP), Republic of Korea [R7117-16-0165, 2016-0-00136-002] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
  4. National Research Foundation of Korea [22A20130012145] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

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This paper presents a CMOS smart temperature sensor using a switched Vernier time-to-digital converter to achieve an energy-efficient temperature sensing. The proposed temperature sensor employs two switched ring oscillators (SROs), of which the oscillation frequencies are slightly different from each other and varying linearly with temperature due to the deployment of a proportional-to-absolute-temperature current generator. The frequencies of the two SROs are measured by counting the rising edges with two counters, and hence, the frequency difference corresponding to temperature can be readily monitored with the digital numbers. A control strategy that switches OFF the ring oscillators after each sampling is developed, such that significant power saving is achieved. The proposed temperature sensor shows a measured resolution of 0.048 degrees C from -20 degrees C to 120 degrees C with 100-ms conversation time. With 1-kHz sampling rate, the power consumption is as small as 93.6 mu W, resulting in 93.6 nJ per sampling. The chip area is 0.118 mm(2) in a standard 0.18-mu m CMOS process.

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