Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 52, Issue 12, Pages 3219-3234Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2747128
Keywords
Analog-to-digital converter; continuous-time (CT) ADC; oversampling ADC; pipeline ADC; residue cancellation
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An oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and -164 dBFS/Hz average small-signal noise density is presented. In contrast to traditional discrete-time (DT) pipeline ADCs, the system processes the signals in CT form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high-peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved DT pipeline ADCs since CT signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28-nm CMOS process technology and consumes 2.3 W.
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