Journal
IEEE ELECTRON DEVICE LETTERS
Volume 38, Issue 7, Pages 918-921Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2017.2703304
Keywords
p-GaN; AlGaN/GaN HEMTs; GaN-on-SOI; 200V; trench isolation; monolithic integration
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Funding
- Electronic Component Systems for European Leadership Joint Undertaking [662133]
- European Union
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Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved. This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size.
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