Journal
IEEE ELECTRON DEVICE LETTERS
Volume 38, Issue 12, Pages 1763-1766Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2017.2768602
Keywords
Single-layer MoS2; encapsulation; reliability; charged traps; hysteresis; bias-temperature instabilities
Categories
Funding
- FWF [I2606-N30]
- NSF EFRI 2-DARE Grant [154288]
- AFOSR [FA9550-14-1-0251]
- Emerging Frontiers & Multidisciplinary Activities
- Directorate For Engineering [1542883] Funding Source: National Science Foundation
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We report considerable improvement in the hysteresis and reliability of single-layer MoS2 field-effect transistors (FETs) achieved by chemical vapor deposition (CVD) of MoS2 and dielectric encapsulation. Our results show that a high-quality 15-nm thick Al2O3 layer allows for an efficient protection of the devices from adsorbent-type trapping sites. Combined use of the CVD-grown MoS2 as a channel and encapsulation simultaneously leads to at least an order of magnitude smaller hysteresis and up to two orders of magnitude lower long-term drifts of the transistor characteristics. Together with high on/off current ratios (similar to 10(9)) achieved in our devices, this presents a considerable advance in the technology of MoS2 FETs. As such, we conclude that both CVD growth of MoS2 and encapsulation present important technological steps toward reaching commercial quality standards of next-generation two-dimensional (2D) material technologies.
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