4.6 Article

Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware

Journal

IEEE ELECTRON DEVICE LETTERS
Volume 38, Issue 9, Pages 1228-1231

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2017.2730959

Keywords

Neural network acceleration; resistive RAM; I-V nonlinearity

Funding

  1. Ministry of Science, ICT and Future Planning, Korea, through the ICT Consilience Creative Program [IITP-R0346-16-1007]
  2. National Research Foundation of Korea
  3. Ministry of Science, ICT and Future Planning, through the Nano-Material Technology Development Program [NRF-2016M3A7B4910249]
  4. Ministry of Trade, Industry and Energy, Korea, through the Industrial Technology Innovation Program [10067764]
  5. Korea Evaluation Institute of Industrial Technology (KEIT) [10067764] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
  6. National Research Foundation of Korea [2016M3A7B4910249] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

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Artificial neural network (ANN) computations based on graphics processing units (GPUs) consume high power. Resistive random-access memory (RRAM) has been gaining attention as a promising technology for implementing power-efficient ANNs, replacing GPU. However, nonlinear I-V characteristics of RRAM devices have been limiting its use for ANN implementation. In this letter, we propose a method and a circuit to address issues due to the nonlinear I-V characteristics. We demonstrate the feasibility of the method by simulating its application to multiple neural networks, from multi-layer perceptron to deep convolutional neural network based on a typical RRAM model. Results from classifying datasets including ImageNet show that the proposed method produces much higher accuracy than the naive linear mapping for a wide range of nonlinearity.

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