Journal
IEEE ELECTRON DEVICE LETTERS
Volume 38, Issue 4, Pages 461-464Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2017.2675160
Keywords
Flash memories; temperature effects; semiconductor device modeling; semiconductor device reliability
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This letter investigates the major differences between planar (2-D) and vertical-channel (3-D) NAND Flash memory arrays in terms of their temperature dependences. Attention is focused on three relevant parameters for memory array operation, namely, cell threshold-voltage, string saturation current, and width of the random telegraph noise distribution. Results highlight that the transition from 2-D to 3-D arrays introduced non-negligible changes in the temperature behavior of these parameters, whose origin is traced back to the different channel material of the technologies, i.e., monocrystalline versus polycrystalline silicon.
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