Journal
2020 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC)
Volume -, Issue -, Pages 259-262Publisher
IEEE
DOI: 10.1109/rfic49505.2020.9218433
Keywords
CMOS; mmW; Frequency Multiplier; Pulsed Oscillator; Injection Locking
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This paper describes a high order programmable frequency multiplier in the 60 GHz band. The circuit implements four chains that can address simultaneously four different frequencies of the IEEE 802.11ay standard and aims to channel bonding, full duplex, or MIMO systems. It is fabricated in a 45nm CMOS PDSOI technology. Each chain consumes 32.6mW and achieves lower than 178fsec of integrated jitter (in the band 10KHz-1.08GHz) for all synthesized frequencies.
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