SoIC for Low-Temperature, Multi-Layer 3D Memory Integration

A low-temperature System-on-Integrated-Chip (LT-SoIC) technology has been successfully applied to multi-layer 3D memory cube integration, which enables high bandwidth, low power and small footprint memory for future HPC applications. In addition, using the technology, each memory layer can be thinned to required thickness to maintain total height while supporting more layer counts. Two LT-SoIC processes were presented. One is through-via reveal last and the other one is through-via reveal first. The through-via revealing of each stacked die is one of the most critical process steps. Various conditions of planarization on chip backside after the through-via revealing were studied to mitigate the corner or edge rounding issue, as it may cause poor bonding. By improving the back-side revealing process, we can achieve good bonding for multi-layer stacking, including DRAM stacking with 4-Hi/ 8-Hi/ 12-Hi, and SRAM stacking with 4-Hi, using the LT-SoIC technology. The bonding quality of the LT-SoIC is measured using I-V curve and shear stress equipment. Linear I-V curve was obtained to show it is an Ohmic contact and the bonding strength of >2.5J/m(2) was measured to show good bonding force. The through-via chain resistances for 4-Hi SRAM and 4/8/12-Hi DRAM and the breakdown voltage for 8/12-Hi DRAM were measured, too. Reliable results were obtained to indicate the integrity of the through-via chains. After that, the bandwidth density and power consumption between typical 3D memory and the SoIC memory were compared. High bandwidth density and low power consumption are obtained in the SoIC memory. Clear advantages of the SoIC CoW stacking technology are realized for multi-layer memory stacking at low temperature.