Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-bitcell SRAM in 10nm FinFET CMOS

A 1.09Mb, high density (HD), 1R1W 8T-bitcell SRAM is demonstrated in 10nm FinFET CMOS featuring Low Swing (LS) and Column Multiplexed (CM) bitline (BL) techniques. Read-Vmin and noise-tolerance is improved using a series NMOS clipper and a split input NAND for early keeper turnoff. Measurements show 30(40)mV lower read-Vmin, 18(30)% lower BL power for the proposed LS(LS+CM) BL schemes, with improved noise tolerance, and minimal area overhead.