Journal
PROCEEDINGS OF THE 2020 32ND INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD 2020)
Volume -, Issue -, Pages 166-169Publisher
IEEE
DOI: 10.1109/ispsd46842.2020.9170032
Keywords
4H-SiC; SJ-VMOSFET; double RESURF JTE; avalanche breakdown; process robustness; TCAD simulation; oxide charge density; charge unbalance
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We have demonstrated 4H-SiC super junction V-groove MOSFETs (SJ-VMOSFETs) with an extremely low specific on-resistance (R-on,R- (sp)) of 0.67 m Omega cm(2) and with a high blocking voltage (V-B) of 1170 V [1]. We have adopted double reduced surface junction termination extensions (DR-JTEs) as a new edge termination for the SJ-VMOSFETs in order to deplete the highly doped drift layer and current spreading layer (CSL) over 1x10(17) cm(-3). We evaluated the process robustness of the DR-JTEs and other conventional edge terminations by using TCAD simulation.
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